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SMPS MOSFET
PD - 95122
IRFB13N50APBF
HEXFET(R) Power MOSFET
Applications l Switch Mode Power Supply (SMPS) l Uninterruptible Power Supply l High Speed Power Switching l Lead-Free
VDSS
500V
RDS(on) max
0.450
ID
14A
Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case ) Mounting torqe, 6-32 or M3 screw
Max.
14 9.1 56 250 2.0 30 9.2 -55 to + 150 300 10
Units
A W W/C V V/ns
C lbf*in (1.1N*m)
Avalanche Characteristics
Symbol
EAS IAR EAR
Parameter
Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Typ.
--- --- ---
Max.
560 14 25
Units
mJ A mJ
Thermal Resistance
Parameter
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
--- 0.50 ---
Max.
0.50 --- 62
Units
C/W
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1
3/18/04
IRFB13N50APBF
Static @ TJ = 25C (unless otherwise specified)
Symbol V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) IDSS IGSS
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. Typ. Max. Units Conditions 500 --- --- V VGS = 0V, ID = 250A --- 0.55 --- V/C Reference to 25C, I D = 1mA --- --- 0.450 VGS = 10V, ID = 8.4A 2.0 --- 4.0 V VDS = VGS, ID = 250A --- --- 25 VDS = 500V, VGS = 0V A --- --- 250 VDS = 400V, VGS = 0V, TJ = 125C --- --- 100 VGS = 30V nA --- --- -100 VGS = -30V Min. 8.1 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- --- --- --- 15 39 39 31 1910 290 11 2730 82 160 Max. Units Conditions --- S VDS = 50V, ID = 8.4A 81 ID = 14A 20 nC VDS = 400V 36 VGS = 10V, See Fig. 6 and 13 --- VDD = 250V --- ID = 14A ns --- R G = 7.5 --- VGS = 10V,See Fig. 10 --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 400V, = 1.0MHz --- VGS = 0V, VDS = 0V to 400V Conditions MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25C, IS = 14A, VGS = 0V TJ = 125C, IF = 14A di/dt = 100A/s
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Symbol IS
ISM
Diode Characteristics
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Reverse RecoveryCurrent Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- 14 A 56
D
S
VSD trr Q rr iRRM ton Notes:
--- --- 1.5 V --- 370 550 ns --- 4.4 6.5 C --- 21 31 A Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11) Starting TJ = 25C, L = 5.7mH, RG = 25, IAS = 14A, dv/dt = 7.6V/ns. (See Figure 12a)
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
ISD 14A, di/dt 250A/s, VDD V(BR)DSS,
TJ 150C.
2
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IRFB13N50APBF
100
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
100
TOP
10
I D, Drain-to-Source Current (A)
BOTTOM
I D, Drain-to-Source Current (A)
BOTTOM
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
10
1
4.5V
4.5V
1
0.1
0.01 0.1 1
20s PULSE WIDTH T J= 25 C
10 100
0.1 0.1 1
20s PULSE WIDTH T J= 150 C
10 100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
I D = 14A
2.5
RDS(on) , Drain-to-Source On Resistance
TJ = 150 C
I D, Drain-to-Source Current (A)
10
2.0
(Normalized)
1.5
TJ = 25 C
1
1.0
0.5
0.1 4 6 8 10
V DS 50V = 20s PULSE WIDTH 12 14 16
0.0 -60 -40 -20 0 20 40 60 80 100
V GS = 10V
120 140 160
V GS, Gate-to-Source Voltage (V)
TJ , Junction Temperature
( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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IRFB13N50APBF
100000 VGS = 0V, f = 1 MHZ Ciss = C + C , C gs gd ds SHORTED Crss = C gd Coss = C + Cgd ds
12
I D = 14A
10000
10
VDS = 400V VDS = 250V VDS = 100V
Ciss
1000
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
7
Coss
100
5
10
Crss
2
1 1 10 100 1000
0 0 12 24 36 48 60
VDS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
100
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
I SD , Reverse Drain Current (A)
TJ = 150 C
10
ID, Drain-to-Source Current (A)
100
10
100sec 1msec
TJ = 25 C
1
1 Tc = 25C Tj = 150C Single Pulse 10 100 10msec
0.1 0.2 0.5 0.8
V GS = 0 V
1.1 1.4
0.1
V SD,Source-to-Drain Voltage (V)
1000
10000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFB13N50APBF
15
V DS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
12
D.U.T.
+
-VDD
I D , Drain Current (A)
9
6
Fig 10a. Switching Time Test Circuit
3
VDS 90%
0 25 50 75 100 125 150
TC , Case Temperature
( C)
Fig 9. Maximum Drain Current vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1
(Z thJC )
D = 0.50
0.1
0.20 0.10
Thermal Response
0.05 0.02 0.01 0.01
SINGLE PULSE (THERMAL RESPONSE)
P DM t1 t2 Notes: 1. Duty factor D = 2. Peak T t1/ t 2 +TC 1
J = P DM x Z thJC
0.001 0.00001
0.0001
0.001
0.01
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFB13N50APBF
1150
ID TOP 6.3A 8.9A 14A
920
BOTTOM
EAS , Single Pulse Avalanche Energy (mJ)
15V
690
VDS
L
DRIVER
460
RG
20V
D.U.T
IAS
+ - VDD
A
230
tp
0.01
Fig 12c. Unclamped Inductive Test Circuit
0 25 50 75 100 125 150
Starting Tj, Junction Temperature
( C)
Fig 12a. Maximum Avalanche Energy vs. Drain Current
tp
V(BR)DSS
I AS
Fig 12d. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K 12V .2F .3F
QG
VGS
D.U.T. + V - DS
QGS VG
QGD
VGS
3mA
IG
ID
Current Sampling Resistors
Charge
Fig 13a. Gate Charge Test Circuit
Fig 13b. Basic Gate Charge Waveform
6
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IRFB13N50APBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs
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IRFB13N50APBF
TO-220AB Package Outline
2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240)
Dimensions are shown in millimeters (inches)
-B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048)
4 15.24 (.600) 14.84 (.584)
1.15 (.045) MIN 1 2 3
LEAD ASSIGNMENTS IGBTs, CoPACK 1 - GATE 21- GATE DRAIN 1- GATE 32- DRAINSOURCE 2- COLLECTOR 3- SOURCE 3- EMITTER 4 - DRAIN
LEAD ASSIGNMENTS
HEXFET
14.09 (.555) 13.47 (.530)
4- DRAIN
4.06 (.160) 3.55 (.140)
4- COLLECTOR
3X 3X 1.40 (.055) 1.15 (.045)
0.93 (.037) 0.69 (.027) M BAM
3X
0.55 (.022) 0.46 (.018)
0.36 (.014)
2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
2.92 (.115) 2.64 (.104)
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010 LOT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB LY L INE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y LOT CODE PAR T NU MB E R
Note: "P" in assembly line position indicates "Lead-Free"
DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.03/04
8
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